1. Field of the Invention
The present invention relates to a semiconductor device and particularly relates to a CMIS device forming a silicon large scale-integrated circuit to achieve high-grade information processing.
2. Description of the Related Art
Silicon large scale-integrated circuit is one of basic techniques for supporting the future high-grade information-driven society. High performance of a CMIS device, which is a constituent element of an integrated circuit, is required for making the function of the integrated circuit high. Although performance of an element has been fundamentally made high by a proportionally scaling rule, there is a situation where recent various physical limits have made it difficult to increase performance based on the very fine structure of the element and operate the element per se. One of difficulties is a problem that the effective thickness of an insulating film is prevented from being reduced due to depletion of a polycrystalline Si gate electrode. Although high performance of an MIS device has been achieved by reduction in thickness of a gate insulating film in accordance with the proportionally scaling rule, higher performance of the MIS device is becoming difficult due to depletion of the polycrystalline Si gate electrode. The depletion-layer capacitance of the polycrystalline Si gate electrode will reach about 30% of the capacitance of an oxide film in a technical generation in which the thickness of the gate oxide film is smaller than 1 nm.
The depletion-layer capacitance can be reduced when the polycrystalline Si gate electrode is replaced by a metal gate electrode. A large issue in use of the metal electrode in the MIS device is a gate processing technique. Technical development of an RIE process is required so newly that metal can be processed with accuracy of the order of tens of nanometers. Particularly in a CMIS device, two kinds of electrode materials different in work function need to be used in accordance with the conduction type in order to achieve an optimum threshold voltage. Development of processing techniques according to the materials is essential. This requirement brings complication in technical development and fabricating process, so that there is a situation where increase in cost is unavoidable.
To avoid this problem, a polycrystalline Si/metal laminated gate electrode structure having a thin metal layer introduced into only the lower portion of the gate electrode, and polycrystalline Si used on the metal layer has been proposed (e.g. a gate electrode structure of metal [lower layer] and polycrystalline Si [upper layer] has been described in U.S. Pat. No. 6,020,024). When this structure is used, the aforementioned problem of processing can be avoided or reduced so that stress of the metal electrode at the time of heat treatment can be relaxed, and that the upper polycrystalline Si functions as an S/D ion implantation stopper to prevent ions from being injected into the channel. When this structure is applied to the gate electrode, a new depletion layer is however generated in the polycrystalline Si/metal Schottky interface. Therefore, suppression of depletion of the gate electrode, which is the original purpose of introduction of the metal gate, cannot be achieved.